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Paiz Gatica, Carlos Vladimir: Dynamically reconfigurable hardware for embedded control systems. 2012
Inhalt
Abstract
1 Introduction
1.1 Contributions
1.2 Thesis Outline
2 Realisation of Digital Control
2.1 Digital Control
2.1.1 Software-Based Design
2.1.2 ASIC-Based Design
2.2 Reconfigurable Hardware
2.2.1 Field Programmable Gate Array
2.2.2 General FPGA-Based Design Flow
2.3 Utilisation of Reconfigurable Hardware for Digital Control
2.3.1 Application Spectrum
2.3.2 Factors of the Technology Migration
2.3.3 Coupling of Reconfigurable Hardware and Software Architectures
2.3.4 Run-Time Hardware Reconfiguration
2.4 Summary
3 Technology Comparison of Reconfigurable Hardware and Software Architectures
3.1 Algorithmic Characterisation
3.1.1 Controller Representation: Cyclic Data Flow Graph
3.1.2 Scheduling of a CDFG
3.1.3 Basic Operations Set: Selection and Weighting
3.1.4 Normalised Operations and Steps
3.1.5 Average Parallelism
3.2 Resource Utilisation Assessment
3.2.1 Computational Density
3.2.2 Energy Efficiency
3.3 Computing Architectures
3.3.1 PowerPC 750-G Processor
3.3.2 FPGA Device
3.4 Realisation Flow
3.4.1 Hardware Implementation-Flow
3.4.2 Software Implementation-Flow
3.5 Benchmarks
3.5.1 PID Controller
3.5.2 State-Feedback Controller
3.5.3 State Observer
3.6 Summary
4 Run-Time Hardware Reconfiguration
4.1 Controller Adjustment
4.2 Run-Time Hardware Reconfiguration
4.2.1 Configuration Granularity
4.2.2 Configuration Interface
4.2.3 Partial Reconfiguration Process
4.2.4 Partition and Placement Approaches
4.2.5 Communication Infrastructure
4.3 Control Adjustment Through Run-Time Reconfiguration
4.3.1 Structure Adaptation
4.3.2 Parameter Adaptation
4.4 Implementation Examples
4.4.1 The RAPTOR System
4.4.2 System Architecture
4.4.3 Inverted Pendulum System
4.4.4 Self-Optimising Motion Controller
4.5 Summary
5 Design Verification through Hardware-in-the-Loop Simulations
5.1 Classification of Test-Systems
5.1.1 Model- and Software-in-the-Loop
5.1.2 Rapid Prototyping
5.1.3 Hardware-in-the-Loop Simulation
5.1.4 On-Line Test
5.1.5 FPGA-in-the-Loop
5.2 HiLDE: HiL Design Environment
5.2.1 Hardware Components
5.2.2 Software Components
5.2.3 Communication and Performance
5.2.4 HilDE Tool Flow
5.2.5 Implementation Examples
5.3 HiLDEGART: HiL Design Environment for Guided Active Real-Time Test
5.3.1 Hardware Components
5.3.2 Software Components
5.3.3 HiLDEGART Tool Flow
5.3.4 HiLDEGART Implementation Examples
5.4 Summary
6 Summary and Outlook
6.1 Summary
6.2 Outlook
Author's Publications
Bibliography
List of Figures
List of Tables
Glossary