In this paper, an implementation of a RISC processor core for SoC designs is presented. We analyze

the differences between a prototypical FPGA implementation and standard cell realizations

in an 0.6μm and an 0.13μm technology, respectively. The core was developed by using

the hardware description language VHDL, which offers the opportunity of adding special, optimized

hardware blocks for various operations. The effects on area and power consumption as

well as computational power are analyzed. A detailed overview of the implementation of additional

hardware multipliers and their effects on the above mentioned topics concludes this paper.