TY  - JOUR
AB  - The secure transmission of data plays a significant
role in todays information era. Especially in the area
of public-key-cryptography methods, which are based on elliptic curves (ECC), gain more and more importance. Compared to asymmetric algorithms, like RSA, ECC can be used with shorter key lengths, while achieving an equal level of security. The performance of ECC-algorithms can be increased significantly by adding application specific hardware extensions.
Due to their fine grained parallelism, VLIW-processors
are well suited for the execution of ECC algorithms. In
this work, we extended the fourfold parallel CoreVA-VLIW-architecture by several hardware accelerators to increase the resource efficiency of the overall system. For the designspace exploration we use a dual design flow, which is based on the automatic generation of a complete C-compiler based tool chain from a central processor specification. Using the hardware accelerators the performance of the scalar multiplication on binary fields can be increased by the factor of 29. The energy consumption can be reduced by up to 90%. The extended processor hardware was mapped on a current 65 nm low-power standard-cell-technology. The chip area of the CoreVA-VLIW-architecture is 0.24mm2 at a power consumption
of 29 mW/MHz. The performance gain is analyzed in respect to the increased hardware costs, as chip area or
power consumption.
DA  - 2010
DO  - 10.5194/ars-8-295-2010
LA  - eng
M2  - 295
PY  - 2010
SN  - 1684-9973
SP  - 295-305
T2  - Advances in Radio Science
TI  - Resource Efficiency of Hardware Extensions of a 4-issue VLIW Processor for Elliptic Curve Cryptography
UR  - https://nbn-resolving.org/urn:nbn:de:0070-pub-20185412
Y2  - 2024-11-22T09:53:16
ER  -