TY  - JOUR
AB  - In this paper we explore different hardware accelerators
for cryptography based on elliptic curves. Furthermore,
we present a hierarchical multiprocessor system-onchip
(MPSoC) platform that can be used for fast integration
and evaluation of novel hardware accelerators. In respect
of two application scenarios the hardware accelerators are
coupled at different hierarchy levels of the MPSoC platform.
The whole system is implemented in a state of the art 65 nm
standard cell technology. Moreover, an FPGA-based rapid
prototyping system for fast system verification is presented.
Finally, a metric to analyze the resource efficiency by means
of chip area, execution time and energy consumption is introduced.
DA  - 2008
DO  - 10.5194/ars-6-259-2008
LA  - eng
M2  - 259
PY  - 2008
SN  - 1684-9965
SP  - 259-264
T2  - Advances in Radio Science
TI  - Hardware Accelerators for Elliptic Curve Cryptography
UR  - https://nbn-resolving.org/urn:nbn:de:0070-pub-22891754
Y2  - 2024-11-24T16:10:14
ER  -