TY  - JOUR
AB  - The growing interest in pulse-mode processing by neural networks is encouraging the development of hardware implementations of massively parallel networks of integrate-and-fire neurons distributed over multiple chips. Address-event representation (AER) has long been considered a convenient transmission protocol for spike based neuromorphic devices. One missing, long-needed feature of AER-based systems is the ability to acquire data from complex neuromorphic systems and to stimulate them using suitable data. We have implemented a general-purpose solution in the form of a peripheral component interconnect (PCI) board (the PCI-AER board) supported by software. We describe the main characteristics of the PCI-AER board, and of the related supporting software. To show the functionality of the PCI-AER infrastructure we demonstrate a reconfigurable multichip neuromorphic system for feature selectivity which models orientation tuning properties of cortical neurons.
DA  - 2007
DO  - 10.1109/TCSI.2007.893509
KW  - asynchronous
KW  - address event representation (AER)
KW  - winner take all (WTA)
KW  - neural chips
KW  - orientation tuning
KW  - cooperative-competitive
KW  - peripheral component interconnect (PCI)-AER
KW  - VLSI
KW  - neuromorphic
KW  - neural networks
LA  - eng
IS  - 5
M2  - 981
PY  - 2007
SN  - 1057-7122
SP  - 981-993
T2  - IEEE-Transactions on Circuits and Systems I: Regular Papers
TI  - A multi-chip pulse-based neuromorphic infrastructure and its application to a model of orientation selectivity
UR  - https://nbn-resolving.org/urn:nbn:de:0070-pub-24265768
Y2  - 2024-11-22T04:02:30
ER  -