TY  - JOUR
AB  - We present a mixed-mode analog/digital VLSI device comprising an array of leaky integrate-and-fire (I&F) neurons, adaptive synapses with spike-timing dependent plasticity, and an asynchronous event based communication infrastructure that allows the user to (re)con figure networks of spiking neurons with arbitrary topologies. The asynchronous communication protocol used by the silicon neurons to transmit spikes (events) off-chip and the silicon synapses to receive spikes from the outside is based on the "address-event representation" (AER). We describe the analog circuits designed to implement the silicon neurons and synapses and present experimental data showing the neuron's response properties and the synapses characteristics, in response to AER input spike trains. Our results indicate that these circuits can be used in massively parallel VLSI networks of I&F neurons to simulate real-time complex spike-based learning algorithms.
DA  - 2006
DO  - 10.1109/TNN.2005.860850
KW  - spike-based learning
KW  - address-event representation (AER)
KW  - neuromorphic circuits
KW  - spike-timing
KW  - analog VLSI
KW  - integrate-and-fire (I &
KW  - F) neurons
KW  - dependent plasticity (STDP)
LA  - eng
IS  - 1
M2  - 211
PY  - 2006
SN  - 1045-9227
SP  - 211-221
T2  - IEEE Transactions on Neural Networks
TI  - A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity
UR  - https://nbn-resolving.org/urn:nbn:de:0070-pub-24265864
Y2  - 2024-11-22T03:12:37
ER  -