TY  - BOOK
AB  - Network Interfaces (NIs) are used in Multiprocessor System-on-Chips (MPSoCs) to connect CPUs to a packet switched Network-on-Chip. In this work we introduce a new NI architecture for our hierarchical CoreVA-MPSoC. The CoreVA-MPSoC targets streaming applications in embedded systems. The main contribution of this paper is a system-level analysis of different NI configurations, considering both software and hardware costs for NoC communication. Different configurations of the NI are compared using a benchmark suite of 10 streaming applications. The best performing NI configuration shows an average speedup of 20 for a CoreVA-MPSoC with 32 CPUs compared to a single CPU. Furthermore, we present physical implementation results using a 28 nm FD-SOI standard cell technology. A hierarchical MPSoC with 8 CPU clusters and 4 CPUs in each cluster running at 800 MHz requires an area of 4.56 mm².
DA  - 2015
DO  - 10.1145/2835512.2835513
LA  - eng
PY  - 2015
SN  - ARRAY(0x7f02290)
TI  - System-Level Analysis of Network Interfaces for Hierarchical MPSoCs
UR  - https://nbn-resolving.org/urn:nbn:de:0070-pub-27831427
Y2  - 2024-11-22T11:07:54
ER  -