In this paper we explore different hardware accelerators

for cryptography based on elliptic curves. Furthermore,

we present a hierarchical multiprocessor system-onchip

(MPSoC) platform that can be used for fast integration

and evaluation of novel hardware accelerators. In respect

of two application scenarios the hardware accelerators are

coupled at different hierarchy levels of the MPSoC platform.

The whole system is implemented in a state of the art 65 nm

standard cell technology. Moreover, an FPGA-based rapid

prototyping system for fast system verification is presented.

Finally, a metric to analyze the resource efficiency by means

of chip area, execution time and energy consumption is introduced.